In many applications it is important to employ integrated devices that are capable of interacting with other electronic apparatuses (for example, a microprocessor that needs to read the data stored in a non-volatile memory).
Referring in particular to the field of memories, different communication protocols have been proposed with respective bus architectures for the communication. Particular attention has been addressed to protocols that allow operating with a low number of signals so as to limit the corresponding number of pins of the integrated device, and thus the cost and size thereof. An example of such protocols is the Low Pin Count (LPC) protocol that provides a communication bus having a reduced number of signal lines for transferring address codes (for accessing memory locations), data (such as words to be read from the memory or to be written into the same) and command codes (for executing a reading or writing operation on the memory), as well as timing and enabling signals. A bus compliant with the LPC standard exploits a time division multiplexing scheme which permits a transfer parallelism typically lower than the transfer parallelism of the memories, which have a plurality of signal lines for the transfer of both the data and the addresses depending on the sizes of the words and of the memory (in terms of number of locations), respectively.
The known integrated devices that are compliant with the LPC standard comprise a communication interface operatively coupled to the memory. Such an interface allows the external electronic apparatus to execute reading and writing operations within a memory location selected by the corresponding address.
A drawback of such integrated devices is the fact that the communication interface reduces the access and transfer rate (because of the address and data multiplexing). Furthermore, the known communication interfaces are not very flexible; this makes it rather complex to employ the integrated devices in some specific applications.
Further, the known integrated devices do not allow the exploitation at their best of the performance of the respective memories, for example, in applications requiring the repetition of consecutive reading or writing operations.